DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 818
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Flash Memory (0.18-µm F-ZTAT Version)
(2)
The on-chip program is automatically downloaded by setting the flash key code register (FKEY)
and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base
register (VBR). The memory MAT is replaced with the embedded program storage area during
download. Since the memory MAT cannot be read during programming/erasing, the procedure
program must be executed in a space other than the flash memory (for example, on-chip RAM).
Since the download result is returned to the programming/erasing interface parameter, whether
download is normally executed or not can be confirmed. The VBR contents can be changed after
completion of download.
(3)
A pulse with the specified period must be applied when programming or erasing. The specified
pulse width is made by the method in which wait loop is configured by the CPU instruction.
Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The
operating frequency of the CPU is set by the programming/erasing interface parameter.
(4)
The start address of the programming destination and the program data are specified in 128-byte
units when programming. The block to be erased is specified with the erase block number in
erase-block units when erasing. Specifications of the start address of the programming destination,
program data, and erase block number are performed by the programming/erasing interface
parameters, and the on-chip program is initiated. The on-chip program is executed by using the
JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip
RAM. The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. All
interrupts are disabled during programming/erasing.
(5)
When processing does not end by 128-byte programming or 1-block erasure, consecutive
programming/erasing can be realized by updating the start address of the programming destination
and program data, or the erase block number. Since the downloaded on-chip program is left in the
on-chip RAM even after programming/erasing completes, download and initialization are not
required when the same processing is executed consecutively.
Rev.1.00 Sep. 08, 2005 Page 768 of 966
REJ09B0219-0100
Download of On-Chip Program
Initialization of Programming/Erasing
Execution of Programming/Erasing
When Programming/Erasing is Executed Consecutively
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