DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 255

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.9.9
In the address/data multiplexed interface, the extension cycles can be inserted before and after the
bus cycle. For details, see section 6.6.6, Extension of Chip Select (CS) Assertion Period.
Figure 6.34 shows an example of the chip select (CS) assertion period extension timing.
Read
Write
Figure 6.34 Chip Select (CS) Assertion Period Extension Timing in Data Cycle
B
Address bus
CSn
AH
RD
D15 to D0
LHWR
LLWR
D15 to D0
BS
RD/WR
DACK
Extension of Chip Select (CS) Assertion Period
Note: n = 3 to 7
T
ma1
Address cycle
Address
Address
T
ma2
T
h
Bus cycle
Rev.1.00 Sep. 08, 2005 Page 205 of 966
T
1
Data cycle
Section 6 Bus Controller (BSC)
Write data
T
2
Read data
REJ09B0219-0100
T
t

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