DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 705

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
5
4
3
2
1
0
Bit Name
EP1 RDFN
EP2 PKTE
EP0s RDFN Undefined W
EP0o RDFN Undefined W
EP0i PKTE
Initial
Value
Undefined W
Undefined W
Undefined 
Undefined W
R/W
Description
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-buffer configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Reserved
The write value should always be 0.
EP0s Read Complete
Write 1 to this bit after data for the EP0s command
FIFO has been read. Writing 1 to this bit enables
transfer of data in the following data stage. A NACK
handshake is returned in response to transfer
requests from the host in the data stage until 1 is
written to this bit.
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Rev.1.00 Sep. 08, 2005 Page 655 of 966
Section 15 USB Function Module (USB)
REJ09B0219-0100

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