DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 263

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4)
If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set
to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external
access (n = 0 to 7).
Figure 6.40 shows an example of the operation in this case. In this example, bus cycle A is a
single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is
not inserted, and a conflict occurs in bus cycle B between the external device write data and this
LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Figure 6.40 Example of Idle Cycle Operation (Write after Single Address Transfer Write)
B
Address bus
CS (area A)
CS (area B)
LLWR
DACK
Data bus
External Access after Single Address Transfer Write
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS3 = 0)
T
2
Output floating
time is long.
T
3
Bus cycle B
T
1
T
2
Data conflict
T
Rev.1.00 Sep. 08, 2005 Page 213 of 966
Bus cycle A
1
(IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0)
T
2
(b) Idle cycle inserted
Section 6 Bus Controller (BSC)
T
3
T
Bus cycle B
i
REJ09B0219-0100
T
1
T
2