DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 672

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
(1)
During transmission, the output signals from the SCI (UART frames) are converted to IR frames
using the IrDA interface (see figure 14.37).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
IrCR.
The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20
MHz, a high-level pulse width of 1.6 µs can be specified because it is the smallest value in the
range greater than 1.41 µs.
For serial data of level 1, no pulses are output.
(2)
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to SCI. 0 is output when the high level pulse is detected while 1 is output when no pulse
is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41
µs is also regarded as a 0 signal.
Rev.1.00 Sep. 08, 2005 Page 622 of 966
REJ09B0219-0100
Transmission
Reception
Transmission
Bit
cycle
Start
bit
Start
bit
Figure 14.37 IrDA Transmission and Reception
0
0
1
1
0
0
UART frame
IR frame
1
1
0
0
Data
Data
0
0
Reception
1
1
Pulse width is 1.6 µs to
3/16 bit cycle
1
1
0
0
Stop
bit
Stop
bit
1
1