DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 495

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
(a)
Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel
3, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B.
As buffer operation has been set, when compare match A occurs, the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details on PWM modes, see section 10.4.5, PWM Modes.
Examples of Buffer Operation
When TGR is an output compare register
TGRB_3
TGRA_3
H'0000
TGRC_3
TGRA_3
TIOCA3
TCNT value
Transfer
H'0200
H'0200
Figure 10.15 Example of Buffer Operation (1)
H'0200
H'0450
H'0450
H'0450
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.1.00 Sep. 08, 2005 Page 445 of 966
H'0520
REJ09B0219-0100
H'0520
Time