DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 1011

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Numerics
0-output and 1-output ............................. 438
16-bit access space.................................. 170
16-bit counter mode................................ 523
16-bit timer pulse unit (TPU) ................. 395
8-bit access space.................................... 169
8-bit timers (TMR) ................................. 501
A
A/D conversion accuracy........................ 747
A/D converter ......................................... 735
Absolute accuracy................................... 747
Acknowledge .......................................... 718
Address error ............................................ 80
Address map ............................................. 69
Address modes........................................ 255
Address/data multiplexed I/O
interface .......................................... 163, 198
All-module-clock-stop mode .......... 854, 870
Area 0 ..................................................... 164
Area 1 ..................................................... 165
Area 2 ..................................................... 165
Area 3 ..................................................... 166
Area 4 ..................................................... 166
Area 5 ..................................................... 167
Area 6 ..................................................... 168
Area 7 ..................................................... 168
Area division........................................... 158
Asynchronous mode ............................... 586
AT-cut parallel-resonance type............... 848
Available output signal and settings
in each port ............................................. 378
Average transfer rate generator............... 544
Index
B
Bφ clock output control........................... 874
Basic bus interface .......................... 162, 172
Big endian ............................................... 161
Bit rate..................................................... 569
Bit synchronous circuit ........................... 732
Block diagram............................................. 2
Block structure ........................................ 765
Block transfer mode ........................ 261, 329
Boot mode....................................... 763, 789
Bulk-in transfer ....................................... 688
Bulk-out transfer ..................................... 687
Burst access mode................................... 267
Burst ROM interface....................... 162, 193
Bus access modes.................................... 266
Bus arbitration......................................... 224
Bus configuration.................................... 150
Bus controller (BSC)............................... 125
Bus cycle division ................................... 323
Bus width ................................................ 161
Byte control SRAM interface ......... 162, 185
C
Cascaded connection............................... 523
Cascaded operation ................................. 447
Chain transfer.......................................... 330
Chip select signals................................... 159
Clock pulse generator ............................. 843
Clock synchronization cycle (Tsy).......... 152
Clocked synchronous mode .................... 603
Communications protocol ....................... 818
Compare match A ................................... 521
Compare match B ................................... 522
Compare match count mode ................... 524
Compare match signal............................. 521
Control transfer ....................................... 681
Rev.1.00 Sep. 08, 2005 Page 961 of 966
REJ09B0219-0100