DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 205

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5
6.5.1
Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions
on each interface.
Table 6.2
Name
Bus cycle start
Address strobe/
address hold
Read strobe
Read/write
Low-high write/
lower-upper byte
select
Low-low write/
lower-lower byte
select
External Bus
Input/Output Pins
Pin Configuration
Symbol
BS
AS/AH
RD
RD/WR
LHWR/LUB Output
LLWR/LLB
Output
Output
Output
Output
Output
I/O
Function
Signal indicating that the bus cycle has started
•
•
Strobe signal indicating that the basic bus, byte
control SRAM, burst ROM, or address/data
multiplexed I/O space is being read
•
•
•
•
•
•
Strobe signal indicating that the basic bus, byte
control SRAM, or burst ROM space is accessed
and address output on address bus is enabled
Signal to hold the address during access to the
address/data multiplexed I/O interface
Signal indicating the input or output direction
Write enable signal of the SRAM during access
to the byte control SRAM space
Strobe signal indicating that the basic bus, burst
ROM, or address/data multiplexed I/O space is
written to, and the upper byte (D15 to D8) of
data bus is enabled
Strobe signal indicating that the byte control
SRAM space is accessed, and the upper byte
(D15 to D8) of data bus is enabled
Strobe signal indicating that the basic bus, burst
ROM, or address/data multiplexed I/O space is
written to, and the lower byte (D7 to D0) of data
bus is enabled
Strobe signal indicating that the byte control
SRAM space is accessed, and the lower byte
(D7 to D0) of data bus is enabled
Rev.1.00 Sep. 08, 2005 Page 155 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100