DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 795

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
17.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 17.4 shows the A/D conversion timing. Table 17.3 indicates
the A/D conversion time.
As indicated in figure 17.4, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in table 17.3.
In scan mode, the values given in table 17.3 apply to the first conversion time. The values given in
table 17.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in
ADCR should be set so that the conversion time is within the ranges indicated by the A/D
conversion characteristics.
SPL
). The length of t
Input Sampling and A/D Conversion Time
D
Address
Write signal
Input sampling
timing
ADF
P
[Legend]
(1):
(2):
t
t
t
D:
SPL
CONV
varies depending on the timing of the write access to ADCSR. The total
:
: A/D conversion time
ADCSR write cycle
ADCSR address
A/D conversion start delay time
Input sampling time
Figure 17.4 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
D
) passes after the ADST bit in ADCSR is set to
t
CONV
CONV
) includes t
Rev.1.00 Sep. 08, 2005 Page 745 of 966
D
and the input sampling time
Section 17 A/D Converter
REJ09B0219-0100

Related parts for DF61654N50FTV