DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 371

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.5
The DTC stores transfer information in the data area. When activated, the DTC reads transfer
information that is stored in the data area and transfers data on the basis of that transfer
information. After the data transfer, it writes updated transfer information back to the data area.
Since transfer information is in the data area, it is possible to transfer data over any required
number of channels. There are three transfer modes: normal, repeat, and block.
The DTC specifies the source address and destination address in SAR and DAR, respectively.
After a transfer, SAR and DAR are incremented, decremented, or fixed independently.
Table 8.2 shows the DTC transfer modes.
Table 8.2
Notes: 1. Either source or destination is specified to repeat area.
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a
single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have
chain transfer performed only when the transfer counter value is 0.
Figure 8.4 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
Transfer
Mode
Normal
Repeat*
Block*
2
2. Either source or destination is specified to block area.
3. After transfer of the specified transfer count, initial state is recovered to continue the
1
Operation
operation.
Size of Data Transferred at
One Transfer Request
1 byte/word/longword
1 byte/word/longword
Block size specified by CRAH (1
to 256 bytes/words/longwords)
DTC Transfer Modes
Memory Address Increment or
Decrement
Incremented/decremented by 1, 2, or 4,
or fixed
Incremented/decremented by 1, 2, or 4,
or fixed
Incremented/decremented by 1, 2, or 4,
or fixed
Section 8 Data Transfer Controller (DTC)
Rev.1.00 Sep. 08, 2005 Page 321 of 966
REJ09B0219-0100
Transfer
Count
1 to 65536
1 to 256*
1 to 65536
3