DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 924

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
22.9
Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for
the corresponding PA7 pin.
Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When
bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock
output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and
the pin becomes an input port.
Tables 22.3 shows the states of the Bφ pin in each processing state.
Table 22.3 Bφ Pin (PA7) State in Each Processing State
Rev.1.00 Sep. 08, 2005 Page 874 of 966
REJ09B0219-0100
DDR
0
1
1
1
Register Setting Value
Bφ Clock Output Control
PSTOP1
X
0
0
1
POSEL1
X
0
1
X
Normal
Operating
State
Hi-Z
Bφ output
Setting
prohibited
High
Sleep
Mode
Hi-Z
Bφ output
Setting
prohibited
High
All-
Module-
Clock-
Stop Mode OPE = 0
Hi-Z
Bφ output
Setting
prohibited
High
Hi-Z
High
Setting
prohibited
High
Software Standby
Mode
OPE = 1
Hi-Z
High
Setting
prohibited
High
Hi-Z
Hi-Z
Hardware
Standby
Mode
Hi-Z
Setting
prohibited