DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 358

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
Rev.1.00 Sep. 08, 2005 Page 308 of 966
REJ09B0219-0100
DTC activation request
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERE,
DTCERG, and DTCERH:
DTCCR:
DTCVBR:
[Legend]
CPU interrupt request
Interrupt source clear
DTCERG, and DTCERH
DTCERA to DTCERE,
Interrupt controller
vector number
DTCCR
request
(memory mapped)
must be set to 1.
External device
External
memory
8
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to E, G, and sH
DTC control register
DTC vector base register
peripheral
On-chip
On-chip
On-chip
module
ROM
RAM
Figure 8.1 Block Diagram of DTC
Bus controller
DTCVBR
REQ
ACK
DTC
Activation
Register
Interrupt
control
control
control
Bus interface
MRA
MRB
SAR
DAR
CRA
CRB