DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 270

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.11.3
Figure 6.43 shows the timing for transition to the bus released state.
Rev.1.00 Sep. 08, 2005 Page 220 of 966
REJ09B0219-0100
[1] A low level of the BREQ signal is sampled at the rising edge of the B signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
B
Address bus
Data bus
CSn
AS
RD
LHWR, LLWR
BREQ
BACK
BREQO
more after the low level of the BREQ signal is sampled.
bit is set to 1, the BREQO signal goes low.
Transition Timing
Figure 6.43 Bus Released State Transition Timing
External space
access cycle
[1]
T
1
T
2
[2]
[3]
[4]
External bus released state
[7]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[5]
[8]
[6]
CPU cycle

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