DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 612

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
• When SMIF in SCMR = 1
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Rev.1.00 Sep. 08, 2005 Page 562 of 966
REJ09B0219-0100
Bit
7
6
Note: * Only 0 can be written, to clear the flag.
Bit
Bit Name
Initial Value
R/W
Bit Name
TDRE
RDRF
R/(W)*
TDRE
7
1
Initial
Value
1
0
R/(W)*
RDRF
6
0
R/W
R/(W)* Transmit Data Register Empty
R/(W)* Receive Data Register Full
R/(W)*
ORER
5
0
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Indicates whether receive data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
Note that when the next serial reception is completed
while the RDRF flag is being set to 1, an overrun error
occurs and the received data is lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing
DMAC or DTC to write data to TDR
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
When an RXI interrupt request is issued allowing
DMAC or DTC to read data from RDR
R/(W)*
ERS
4
0
R/(W)*
PER
3
0
TEND
R
2
1
MPB
R
1
0
MPBT
R/W
0
0