DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 323

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode.
In figure 7.19, the source address side is specified to the repeat area by DACR and the offset
addition is selected. The offset value is set to 4 × data access size (when the data access size is
longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access
size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an
example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address.
A repeat size end interrupt is requested when the repeat size of transfers is completed.
Offset
Offset
Offset
Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
XY Conversion Using Offset
Data 1
Data 2
Data 3
Data 4
1st transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 5
Data 6
Data 7
Data 8
Interrupt
request
generated
Address
initialized
Data 9
Data 10
Data 11
Data 12
2nd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Data 13
Data 14
Data 15
Data 16
Transfer source
addresses
changed
by CPU
Transfer
Interrupt
request
generated
Address
initialized
1st transfer
2nd transfer
3rd transfer
4th transfer
3rd transfer
Data 1
Data 5
Data 9
Data 13
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Data 16
Rev.1.00 Sep. 08, 2005 Page 273 of 966
Data 1
Data 5
Data 13
Data 9
Transfer source
addresses
changed
by CPU
Interrupt
request
generated
Transfer
Section 7 DMA Controller (DMAC)
Data 2
Data 6
Data 10
Data 14
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Data 16
Data 3
Data 7
Data 11
Data 15
REJ09B0219-0100
1st transfer
2nd transfer
3rd transfer
4th transfer
Data 16
Data 4
Data 8
Data 12