DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 127

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.2
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF,
respectively, and all modules except the DTC and DMAC enter module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is canceled.
Interrupts after Reset
On-Chip Peripheral Functions after Reset Release
Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)
(1): Reset exception handling vector address (when reset, (1) = H'000000)
(2): Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First instruction in the exception handling routine
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
I
RES
Vector
fetch
(1)
(2)
operation
Internal
High
Rev.1.00 Sep. 08, 2005 Page 77 of 966
instruction
prefetch
Section 4 Exception Handling
First
(3)
(4)
REJ09B0219-0100