DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 920

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
After the reset state is cleared, all modules other than the DMAC and DTC and on-chip RAM are
in module stop mode.
The registers of the module for which module stop mode is selected cannot be read from or written
to.
22.7.2
All-Module-Clock-Stop Mode
When the ACSE bit is set to 1 and all modules controlled by MSTPCRA and MSTPCRB are
stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer are
stopped (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), executing a SLEEP instruction with the
SSBY bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit timer* and watchdog
timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-
module-clock-stop mode at the end of the bus cycle.
When power consumption should be reduced ever more in all-module-clock-stop mode, stop
modules controlled by MSTPCRC (MSTPCRC[15:8] = H'FFFF).
All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ11 pins),
RES pin input, or an internal interrupt (8-bit timer* or watchdog timer), and the CPU returns to the
normal program execution state via the exception handling state. All-module-clock-stop mode is
not cleared if interrupts are disabled, if interrupts other than NMI are masked on the CPU side, or
if the relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Note: * Operation or halting of the 8-bit timer can be selected by bits MSTPA9 and MSTPA8 in
MSTPCRA.
Rev.1.00 Sep. 08, 2005 Page 870 of 966
REJ09B0219-0100