DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 248

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.9
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this
LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed
I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly
to this LSI.
6.9.1
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be
specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in
MPXCR.
6.9.2
In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 6.18
shows the relationship between the bus width and address output.
Table 6.18 Address/Data Multiplex
6.9.3
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.
For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,
D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is
accessed, the corresponding address will be output to the address bus.
For details on access size and data alignment, see section 6.5.6, Endian and Data Alignment.
Rev.1.00 Sep. 08, 2005 Page 198 of 966
REJ09B0219-0100
Bus Width
8 bits
16 bits
Address/Data Multiplexed I/O Interface
Address/Data Multiplexed I/O Space Setting
Address/Data Multiplex
Data Bus
Address
Data
Address
Data
Cycle
A15
D15
PI7
-
-
D14
A14
PI6
-
-
A13
D13
PI5
-
-
A12
D12
PI4
-
-
D11
A11
PI3
-
-
A10
D10
PI2
-
-
PI1
A9
D9
-
-
Data Pins
PI0
D8
A8
-
-
PH7
D7
D7
A7
A7
PH6
A6
D6
A6
D6
PH5
D5
D5
A5
A5
PH4
D4
D4
A4
A4
PH3
A3
D3
A3
D3
PH2
D2
D2
A2
A2
PH1
D1
D1
A1
A1
PH0
A0
D0
A0
D0