DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 692

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 USB Function Module (USB)
15.3.1
IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.
Rev.1.00 Sep. 08, 2005 Page 642 of 966
REJ09B0219-0100
Bit
7
6
5
4
3
Bit
Bit Name
Initial Value
R/W
Bit Name
BRST
EP1FULL
EP2TR
EP2EMPTY
SETUPTS
Interrupt Flag Register 0 (IFR0)
BRST
R/W
7
0
EP1 FULL
0
Initial
Value
0
0
0
1
R
6
0
R/W
R/W
R
R/W
R
R/W
EP2 TR
R/W
5
0
Setup Command Receive Complete
Description
Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1
as long as there is valid data in the FIFO buffer.
This is a status bit, and cannot be cleared.
EP2 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 2 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet
transmission is enabled.
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit, and cannot be cleared.
This bit is set to 1 when endpoint 0 receives successfully
a setup command requiring decoding on the application
side, and returns an ACK handshake to the host.
EP2 EMPTY
R
4
1
SETUP TS
R/W
3
0
EP0o TS
R/W
2
0
EP0i TR
R/W
1
0
EP0i TS
R/W
0
0