DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 273

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.13.2
This LSI has a write data buffer function for the peripheral module access. Using the write data
buffer function enables peripheral module writes and on-chip memory or external access to be
executed in parallel. The write data buffer function is made available by setting the PWDBE bit in
BCR2 to 1. For details on the on-chip peripheral module registers, see table 6.26, Number of
Access Cycles for Registers of On-Chip Peripheral Modules in section 6.12, Internal Bus.
Figure 6.45 shows an example of the timing when the write data buffer function is used. When this
function is used, if an internal I/O register write continues for two cycles or longer and then there
is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only is
performed in the first two cycles. However, from the next cycle onward an internal memory or an
external access and internal I/O register write are executed in parallel rather than waiting until it
ends.
Write Data Buffer Function for Peripheral Modules
Figure 6.45 Example of Timing when Peripheral Module
I
Internal
address bus
P
Internal I/O
address bus
Internal I/O
data bus
Write Data Buffer Function is Used
Peripheral module write
Peripheral module address
On-chip
memory
read
Rev.1.00 Sep. 08, 2005 Page 223 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100

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