DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 777

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4.6
The logic levels at the SCL and SDA pins are routed through the noise cancelers before being
latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL
(or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
SCL
SCL
User
Sampling clock
Noise Canceler
SDA input
SCL input
or
Figure 16.12 Slave Receive Mode Operation Timing 2
A
9
System clock period
Figure 16.13 Block Diagram of Noise Canceler
Sampling clock
D
Bit 7
1
Latch
C
Bit 6
Data 1
2
Q
Bit 5
3
D
Bit 4
Sampling
4
clock
Latch
C
Bit 3
5
[3] Set ACKBT
Q
Bit 2
6
Rev.1.00 Sep. 08, 2005 Page 727 of 966
Bit 1
7
Compare
detection
Section 16 I
match
circuit
[3] Read ICDRR
Bit 0
8
A
2
C Bus Interface2 (IIC2)
Internal SCL
internal SDA
REJ09B0219-0100
9
or
[4] Read ICDRR
Data 1
Data 2