DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 931

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Register Name
Port I pull-up MOS control register
Port 2 open-drain control register
Port F open-drain control register
Port function control register 0
Port function control register 1
Port function control register 2
Port function control register 4
Port function control register 6
Port function control register 7
Port function control register 9
Port function control register B
Port function control register C
Software standby release IRQ enable
register
DMA source address register_0
DMA destination address register_0
DMA offset register_0
DMA transfer count register_0
DMA block size register_0
DMA mode control register_0
DMA address control register_0
DMA source address register_1
DMA destination address register_1
DMA offset register_1
DMA transfer count register_1
DMA block size register_1
DMA mode control register_1
DMA address control register_1
DMA source address register_2
DMA destination address register_2
DMA offset register_2
DMA transfer count register_2
DMA block size register_2
DMA mode control register_2
DMA address control register_2
DMA source address register_3
Abbreviation
PIPCR
P2ODR
PFODR
PFCR0
PFCR1
PFCR2
PFCR4
PFCR6
PFCR7
PFCR9
PFCRB
PFCRC
SSIER
DSAR_0
DDAR_0
DOFR_0
DTCR_0
DBSR_0
DMDR_0
DACR_0
DSAR_1
DDAR_1
DOFR_1
DTCR_1
DBSR_1
DMDR_1
DACR_1
DSAR_2
DDAR_2
DOFR_2
DTCR_2
DBSR_2
DMDR_2
DACR_2
DSAR_3
Number
of Bits
8
8
8
8
8
8
8
8
8
8
8
8
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
H'FFBB9
H'FFBBC
H'FFBBD
H'FFBC0
H'FFBC1
H'FFBC2
H'FFBC4
H'FFBC6
H'FFBC7
H'FFBC9
H'FFBCB
H'FFBCC
H'FFBCE
H'FFC00
H'FFC04
H'FFC08
H'FFC0C
H'FFC10
H'FFC14
H'FFC18
H'FFC20
H'FFC24
H'FFC28
H'FFC2C
H'FFC30
H'FFC34
H'FFC38
H'FFC40
H'FFC44
H'FFC48
H'FFC4C
H'FFC50
H'FFC54
H'FFC58
H'FFC60
Rev.1.00 Sep. 08, 2005 Page 881 of 966
Module
I/O port
I/O port
INTC
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_0
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_1
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_2
DMAC_3
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Section 23 List of Registers
Data
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
REJ09B0219-0100
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Pφ/3Pφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ