DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 307

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The transfer direction is decided by the DIRS bit in DACR which specifies an external device with
the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an
external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is
transferred from an external device with the DACK pin to an external memory (DDAR). The
settings of registers which are not used as the transfer source or destination are ignored.
The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The
DACK signal is low active.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle.
Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an
example of operation in single address mode.
LSI
Data flow
Figure 7.4 Data Flow in Single Address Mode
DMAC
DREQ
DACK
External
address
bus
External
data
bus
Rev.1.00 Sep. 08, 2005 Page 257 of 966
External device
Section 7 DMA Controller (DMAC)
with DACK
External
memory
REJ09B0219-0100