DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 398

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 I/O Ports
9.1.1
DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from
the DDR is invalid and DDR is always read as an undefined value.
When the general I/O port function is selected, the corresponding pin functions as an output port
by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by
clearing the corresponding DDR bit to 0.
The initial DDR values are shown in table 9.3.
Table 9.3
Rev.1.00 Sep. 08, 2005 Page 348 of 966
REJ09B0219-0100
Port
Port A
Other ports
Bit
Bit Name
Initial Value
R/W
Note: The lower six bits are valid and the upper two bits are reserved for port 6 registers.
The lower four bits are valid and the upper four bits are reserved for port B registers.
The lower five bits are valid and the upper three bits are reserved for port F registers.
The lower three bits are valid and the upper five bits are reserved for port M registers.
Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H, I, and M)
Pn7DDR
Startup Mode and Initial Value
W
7
0
Pn6DDR
W
6
0
External Extended Mode
H'80
Pn5DDR
W
5
0
Pn4DDR
W
4
0
Pn3DDR
W
3
0
Startup Mode
H'00
Pn2DDR
Single-Chip Mode
H'00
W
2
0
Pn1DDR
W
1
0
Pn0DDR
W
0
0