DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 40

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 24 Electrical Characteristics
Figure 24.1 Output Load Circuit ................................................................................................ 921
Figure 24.2 External Bus Clock Timing..................................................................................... 922
Figure 24.3 Oscillation Settling Timing after Software Standby Mode ..................................... 922
Figure 24.4 Oscillation Settling Timing ..................................................................................... 923
Figure 24.5 External Input Clock Timing................................................................................... 923
Figure 24.6 Reset Input Timing.................................................................................................. 924
Figure 24.7 Interrupt Input Timing............................................................................................. 925
Figure 24.8 Basic Bus Timing: Two-State Access ..................................................................... 928
Figure 24.9 Basic Bus Timing: Three-State Access ................................................................... 929
Figure 24.10 Basic Bus Timing: Three-State Access, One Wait................................................ 930
Figure 24.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ............... 931
Figure 24.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ............. 932
Figure 24.13 Byte Control SRAM: Two-State Read/Write Access............................................ 933
Figure 24.14 Byte Control SRAM: Three-State Read/Write Access.......................................... 934
Figure 24.15 Burst ROM Access Timing: One-State Burst Access ........................................... 935
Figure 24.16 Burst ROM Access Timing: Two-State Burst Access........................................... 936
Figure 24.17 Address/Data Multiplexed Access Timing (No Wait)
Figure 24.18 Address/Data Multiplexed Access Timing (Wait Control)
Figure 24.19 External Bus Release Timing ................................................................................ 939
Figure 24.20 External Bus Request Output Timing.................................................................... 939
Figure 24.21 DMAC (DREQ) Input Timing .............................................................................. 940
Figure 24.22 DMAC (TEND) Output Timing............................................................................ 940
Figure 24.23 DMAC Single-Address Transfer Timing: Two-State Access ............................... 941
Figure 24.24 DMAC Single-Address Transfer Timing: Three-State Access ............................. 942
Figure 24.25 I/O Port Input/Output Timing................................................................................ 945
Figure 24.26 TPU Input/Output Timing ..................................................................................... 945
Figure 24.27 TPU Clock Input Timing....................................................................................... 945
Figure 24.28 PPG Output Timing............................................................................................... 945
Figure 24.29 8-Bit Timer Output Timing ................................................................................... 946
Figure 24.30 8-Bit Timer Reset Input Timing ............................................................................ 946
Figure 24.31 8-Bit Timer Clock Input Timing ........................................................................... 946
Figure 24.32 WDT Output Timing ............................................................................................. 946
Figure 24.33 SCK Clock Input Timing ...................................................................................... 946
Figure 24.34 SCI Input/Output Timing: Clocked Synchronous Mode ....................................... 947
Figure 24.35 A/D Converter External Trigger Input Timing...................................................... 947
Figure 24.36 I
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(Basic, Four-State Access)..................................................................................... 937
(Address Cycle Program Wait × 1 + Data Cycle Program Wait × 1 +
Data Cycle Pin Wait × 1)....................................................................................... 938
2
C Bus Interface2 Input/Output Timing (Option) ................................................ 947