DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 765

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
2
1
0
Bit Name
AL
AAS
ADZ
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
Description
Arbitration Lost Flag
This flag indicates that arbitration was lost in master
mode.
When two or more master devices attempt to seize the
bus at nearly the same time, the I
and if the I
the data it sent, it sets AL to 1 to indicate that the bus
has been taken by another master.
[Setting conditions]
•
•
[Clearing condition]
•
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 when the first
frame following a start condition matches bits SVA6 to
SVA0 in SAR.
[Setting conditions]
•
•
[Clearing condition]
•
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
•
[Clearing condition]
•
When the internal SDA and the SDA pin level
disagree at the rising of SCL in master transmit
mode
When the SDA pin outputs a high level in master
mode while a start condition is detected
When 0 is written to this bit after reading AL = 1
When the slave address is detected in slave
receive mode
When the general call address is detected in slave
receive mode
When 0 is written to this bit after reading AAS = 1
When the general call address is detected in slave
receive mode
When 0 is written to this bit after reading ADZ = 1
2
C bus interface detects data differing from
Rev.1.00 Sep. 08, 2005 Page 715 of 966
Section 16 I
2
C bus monitors SDA,
2
C Bus Interface2 (IIC2)
REJ09B0219-0100