DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 421

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.2.7
(1)
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PDnDDR bit settings.
[Legend]
n:
Note:
9.2.8
(1)
The pin function is switched as shown below according to the combination of operating mode, the
EXPE bit, and the PEnDDR bit settings.
[Legend]
n:
Note:
Module Name
Bus controller
I/O port
Module Name
Bus controller
I/O port
PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0
PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8
0 to 7
0 to 7
*
*
Port D
Port E
Address output is enabled by setting PDnDDR = 1 in external extended mode
(EXPE = 1)
Address output is enabled by setting PDnDDR = 1 in external extended mode
(EXPE = 1)
Pin Function
Address output
PDn output
PDn input
(initial setting)
Pin Function
Address output
PEn output
PEn input
(initial setting)
MCU Operating Mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Single-chip mode*
Modes other than on-chip ROM
disabled extended mode
MCU Operating Mode
On-chip ROM disabled extended mode
On-chip ROM enabled extended mode
Single-chip mode*
Modes other than on-chip ROM
disabled extended mode
Rev.1.00 Sep. 08, 2005 Page 371 of 966
Setting
Setting
I/O Port
PDnDDR

1
1
0
I/O Port
PEnDDR

1
1
0
Section 9 I/O Ports
REJ09B0219-0100