DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 223

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.6.3
This section describes the basic timing when the data is specified as big endian.
(1)
Figures 6.14 to 6.16 show the bus timing of 16-bit 2-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles
can be inserted.
Figure 6.14 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)
16-Bit 2-State Access Space
Basic Timing
Read
Write
B
Address
CSn
AS
RD
D15 to D8
D7 to D0
LHWR
LLWR
D15 to D8
D7 to D0
BS
RD/WR
DACK
Notes:
1. n = 0 to 7
2. When RDNn = 0
3. When DKC = 0
T
1
Bus cycle
High level
High-Z
Valid
Rev.1.00 Sep. 08, 2005 Page 173 of 966
T
2
Invalid
Valid
Section 6 Bus Controller (BSC)
REJ09B0219-0100

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