DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 29

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figures
Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 2
Figure 1.2 Pin Assignments ............................................................................................................ 3
Section 2 CPU
Figure 2.1 CPU Operating Modes ................................................................................................ 19
Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 20
Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 20
Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 22
Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 23
Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 24
Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 24
Figure 2.8 Memory Map............................................................................................................... 25
Figure 2.9 CPU Registers ............................................................................................................. 26
Figure 2.10 Usage of General Registers ....................................................................................... 27
Figure 2.11 Stack .......................................................................................................................... 28
Figure 2.12 General Register Data Formats ................................................................................. 32
Figure 2.13 Memory Data Formats............................................................................................... 33
Figure 2.14 Instruction Formats.................................................................................................... 50
Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 56
Section 3 MCU Operating Modes
Figure 3.1 Address Map (1) in each Operating Mode of H8SX/1653 .......................................... 69
Figure 3.1 Address Map (2) in each Operating Mode of H8SX/1653 .......................................... 70
Figure 3.2 Address Map (1) in each Operating Mode of H8SX/1654 .......................................... 71
Figure 3.2 Address Map (2) in each Operating Mode of H8SX/1654 .......................................... 72
Section 4 Exception Handling
Figure 4.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)........................................ 77
Figure 4.2 Reset Sequence
(16-Bit External Access in On-chip ROM Disabled Advanced Mode) ...................... 78
Figure 4.3 Stack Status after Exception Handling ........................................................................ 85
Figure 4.4 Operation when SP Value Is Odd................................................................................ 86
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 88
Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 104
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 111
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 113
Rev.1.00 Sep. 08, 2005 Page xxvii of xlviii