DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 334

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
B
Address
bus
RD
LHWR
LLWR
TEND
B
Address
bus
RD
LHWR
LLWR
TEND
Rev.1.00 Sep. 08, 2005 Page 284 of 966
REJ09B0219-0100
(Transfer Destination DDAR = Odd Address and Destination Address Decrement)
Bus
released
Bus
released
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Source DSAR = Odd Address and Source Address Increment)
4m + 1
read cycle
DMA byte
DMA word
read cycle
4m
4m + 2
DMA word
read cycle
DMA word
read cycle
4m + 2
4m + 4
write cycle
read cycle
DMA byte
DMA byte
4n + 5
DMA word
write cycle
DMA word
write cycle
4n + 6
4n
DMA word
write cycle
write cycle
DMA byte
4n + 8
4n +2
Bus
released
Bus
released
read cycle
DMA word
DMA byte
read cycle
4m + 5
4m + 4
DMA word
read cycle
DMA word
4m + 6
read cycle
4m + 6
Last transfer cycle
Last transfer cycle
4m + 8
write cycle
read cycle
DMA byte
DMA byte
4n + 1
DMA word
write cycle
DMA word
write cycle
4n + 4
4n + 2
m and n are integers.
m and n are integers.
DMA word
write cycle
4n + 6
write cycle
DMA byte
4n + 4
released
released
Bus
Bus