DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 25

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 Operation ........................................................................................................................... 718
16.5 Interrupt Request................................................................................................................ 732
16.6 Bit Synchronous Circuit..................................................................................................... 732
16.7 Usage Notes ....................................................................................................................... 733
Section 17 A/D Converter..................................................................................735
17.1 Features.............................................................................................................................. 735
17.2 Input/Output Pins ............................................................................................................... 737
17.3 Register Descriptions ......................................................................................................... 737
17.4 Operation ........................................................................................................................... 742
17.5 Interrupt Source ................................................................................................................. 747
17.6 A/D Conversion Accuracy Definitions .............................................................................. 747
17.7 Usage Notes ....................................................................................................................... 749
16.3.1 I
16.3.2 I
16.3.3 I
16.3.4 I
16.3.5 I
16.3.6 Slave Address Register (SAR).............................................................................. 716
16.3.7 I
16.3.8 I
16.3.9 I
16.4.1 I
16.4.2 Master Transmit Operation ................................................................................... 719
16.4.3 Master Receive Operation..................................................................................... 721
16.4.4 Slave Transmit Operation ..................................................................................... 723
16.4.5 Slave Receive Operation....................................................................................... 726
16.4.6 Noise Canceler...................................................................................................... 727
16.4.7 Example of Use..................................................................................................... 728
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 738
17.3.2 A/D Control/Status Register (ADCSR) ................................................................ 739
17.3.3 A/D Control Register (ADCR) ............................................................................. 741
17.4.1 Single Mode.......................................................................................................... 742
17.4.2 Scan Mode ............................................................................................................ 743
17.4.3 Input Sampling and A/D Conversion Time .......................................................... 745
17.4.4 External Trigger Input Timing.............................................................................. 746
17.7.1 Module Stop Mode Setting ................................................................................... 749
17.7.2 Permissible Signal Source Impedance .................................................................. 749
17.7.3 Influences on Absolute Accuracy ......................................................................... 749
17.7.4 Setting Range of Analog Power Supply and Other Pins ....................................... 750
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................... 707
C Bus Control Register B (ICCRB).................................................................... 708
C Bus Mode Register (ICMR)............................................................................ 710
C Bus Interrupt Enable Register (ICIER) ........................................................... 711
C Bus Status Register (ICSR)............................................................................. 713
C Bus Transmit Data Register (ICDRT)............................................................. 716
C Bus Receive Data Register (ICDRR).............................................................. 717
C Bus Shift Register (ICDRS)............................................................................ 717
C Bus Format...................................................................................................... 718
Rev.1.00 Sep. 08, 2005 Page xxiii of xlviiil