DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 568

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 8-Bit Timers (TMR)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.
12.4
12.4.1
Figure 12.5 shows an example of the 8-bit timer being used to generate a pulse output with a
desired duty cycle. The control bits are set as follows:
1. Clear the bit CCLR1 in TCR to 0 and set the bit CCLR0 in TCR to 1 so that TCNT is cleared
2. Set the bits OS3 to OS0 in TCSR to B'0110, causing the output to change to 1 at a TCORA
With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a
pulse width determined by TCORB. No software intervention is required. The timer output is 0
until the first compare match occurs after a reset.
Rev.1.00 Sep. 08, 2005 Page 518 of 966
REJ09B0219-0100
Bit
1
0
at a TCORA compare match.
compare match and to 0 at a TCORB compare match.
2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first
3. Available only in unit 0 and unit 1.
Bit Name
OS1
OS0
Operation
Pulse Output
compare match occurs after a reset.
Initial
Value
0
0
R/W
R/W
R/W
Description
Output Select 1 and 0*
These bits select a method of TMO pin output when
compare match A of TCORA and TCNT occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A occurs
(toggle output)
2