DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 26

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 D/A Converter ................................................................................. 753
18.1 Features.............................................................................................................................. 753
18.2 Input/Output Pins............................................................................................................... 754
18.3 Register Descriptions......................................................................................................... 754
18.4 Operation ........................................................................................................................... 757
18.5 Usage Notes ....................................................................................................................... 758
Section 19 RAM ................................................................................................ 759
Section 20 Flash Memory (0.18-µm F-ZTAT Version).................................... 761
20.1 Features.............................................................................................................................. 761
20.2 Mode Transition Diagram.................................................................................................. 763
20.3 Block Structure .................................................................................................................. 765
20.4 Programming/Erasing Interface ......................................................................................... 767
20.5 Input/Output Pins............................................................................................................... 769
20.6 Register Descriptions......................................................................................................... 770
20.7 On-Board Programming Mode .......................................................................................... 789
20.8 Protection........................................................................................................................... 810
20.9 Flash Memory Emulation Using RAM.............................................................................. 813
20.10 Programmer Mode ............................................................................................................. 816
Rev.1.00 Sep. 08, 2005 Page xxiv of xlviii
17.7.5 Notes on Board Design ......................................................................................... 750
17.7.6 Notes on Noise Countermeasures ......................................................................... 750
17.7.7 A/D Input Hold Function in Software Standby Mode .......................................... 751
18.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 754
18.3.2 D/A Control Register 01 (DACR01) .................................................................... 755
18.5.1 Module Stop Mode Setting ................................................................................... 758
18.5.2 D/A Output Hold Function in Software Standby Mode........................................ 758
20.3.1 Block Diagram of H8SX/1653.............................................................................. 765
20.3.2 Block Diagram of H8SX/1654.............................................................................. 766
20.6.1 Programming/Erasing Interface Registers ............................................................ 771
20.6.2 Programming/Erasing Interface Parameters ......................................................... 777
20.6.3 RAM Emulation Register (RAMER).................................................................... 788
20.7.1 SCI Boot Mode ..................................................................................................... 789
20.7.2 USB Boot Mode ................................................................................................... 793
20.7.3 User Program Mode.............................................................................................. 797
20.7.4 On-Chip Program and Storable Area for Program Data ....................................... 807
20.8.1 Hardware Protection ............................................................................................. 810
20.8.2 Software Protection .............................................................................................. 811
20.8.3 Error Protection .................................................................................................... 811

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