DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 306

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
(2)
In single address mode, data between an external device and an external memory is directly
transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in
one bus cycle. In this mode, the data bus width must be the same as the data access size. For
details on the data bus width, see section 6, Bus Controller (BSC).
The DMAC accesses an external device as the transfer source or destination by outputting the
strobe signal (DACK) to the external device with DACK and accesses the other transfer target by
outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4
shows an example of a transfer between an external memory and an external device with the
DACK pin. In this example, the external device outputs data on the data bus and the data is written
to the external memory in the same bus cycle.
Rev.1.00 Sep. 08, 2005 Page 256 of 966
REJ09B0219-0100
Address B
Address T
Single Address Mode
A
A
Figure 7.2 Example of Signal Timing in Dual Address Mode
B
Address bus
RD
WR
TEND
Figure 7.3 Operations in Dual Address Mode
DMA read
Transfer
cycle
DSAR
Address update setting is as follows:
Source address increment
Fixed destination address
DMA write
DDAR
cycle
Address T
B