DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 30

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 5.5 Interrupt Exception Handling.................................................................................... 114
Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 117
Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 122
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 127
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) .......................... 137
Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface,
Figure 6.4 Internal Bus Configuration........................................................................................ 150
Figure 6.5 System Clock: External Bus Clock = 4:1, External 2-State Access .......................... 153
Figure 6.6 System Clock: External Bus Clock = 2:1, External 3-State Access .......................... 154
Figure 6.7 Address Space Area Division.................................................................................... 158
Figure 6.8 CSn Signal Output Timing (n = 0 to 7) ..................................................................... 159
Figure 6.9 Timing When CS Signal is Output to the Same Pin.................................................. 160
Figure 6.10 Access Sizes and Data Alignment Control for 8-Bit Access Space
Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space
Figure 6.12 Access Sizes and Data Alignment Control for 16-Bit Access Space
Figure 6.13 Access Sizes and Data Alignment Control for 16-Bit Access Space
Figure 6.14 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)........... 173
Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) ............ 174
Figure 6.16 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) ......... 175
Figure 6.17 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)........... 176
Figure 6.18 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) .......... 177
Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) ......... 178
Figure 6.20 Example of Wait Cycle Insertion Timing................................................................ 180
Figure 6.21 Example of Read Strobe Timing ............................................................................. 181
Figure 6.22 Example of Timing when Chip Select Assertion Period is Extended ..................... 183
Figure 6.23 DACK Signal Output Timing.................................................................................. 184
Figure 6.24 16-Bit 2-State Access Space Bus Timing................................................................ 187
Figure 6.25 16-Bit 3-State Access Space Bus Timing................................................................ 188
Figure 6.26 Example of Wait Cycle Insertion Timing................................................................ 190
Figure 6.27 DACK Signal Output Timing.................................................................................. 192
Figure 6.28 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)................ 195
Figure 6.29 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) .................. 196
Figure 6.30 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1) ........................... 200
Figure 6.31 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1) ......................... 201
Rev.1.00 Sep. 08, 2005 Page xxviii of xlviii
3-State Access Space, and RDNn = 0)....................................................................... 139
(Big Endian) ............................................................................................................ 169
(Little Endian).......................................................................................................... 170
(Big Endian) ............................................................................................................ 171
(Little Endian).......................................................................................................... 171