DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 141

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.3.2
CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt
exception handling by the CPU can be given priority over that of the DTC and DMAC transfer.
The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of
the DMAC is set by the DMAC control register for each channel.
Bit
7
6
5
4
3
Bit
Bit Name
Initial Value
R/W
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Bit Name
CPUPCE
DTCP2
DTCP1
DTCP0
IPSETE
CPU Priority Control Register (CPUPCR)
CPUPCE
R/W
7
0
Initial
Value
0
0
0
0
0
DTCP2
R/W
6
0
R/W
R/W
R/W
R/W
R/W
R/W
DTCP1
R/W
5
0
CPU Priority Control Enable
Interrupt Priority Set Enable
Description
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DTC and
DMAC.
0: CPU always has the lowest priority
1: CPU priority control enabled
DTC Priority Level 2 to 0
These bits set the DTC priority level.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Controls the function which automatically assigns the
interrupt priority level of the CPU. Setting this bit to 1
automatically sets bits CPUP2 to CPUP0 by the CPU
interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
0: Bits CPUP2 to CPUP0 are not updated automatically
1: The interrupt mask bit value is reflected in bits CPUP2
to CPUP0
DTCP0
R/W
4
0
IPSETE
R/W
3
0
Rev.1.00 Sep. 08, 2005 Page 91 of 966
CPUP2
R/(W)*
2
0
Section 5 Interrupt Controller
CPUP1
R/(W)*
1
0
REJ09B0219-0100
CPUP0
R/(W)*
0
0