DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 789

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.2
ADCSR controls A/D conversion operations.
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit Name
ADF
ADIE
ADST

A/D Control/Status Register (ADCSR)
R/(W)*
ADF
7
0
Initial
Value
0
0
0
0
ADIE
R/W
6
0
R/W
R/(W)* A/D End Flag
R/W
R/W
R
ADST
R/W
5
0
Description
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
When this bit is set to 1, ADI interrupts by ADF are
enabled.
A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or hardware standby mode.
Reserved
This is a read-only bit and cannot be modified.
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels
in scan mode
When 0 is written after reading ADF = 1
When the DMAC or DTC is activated by an ADI
interrupt and ADDR is read
R
4
0
CH3
R/W
3
0
Rev.1.00 Sep. 08, 2005 Page 739 of 966
CH2
R/W
2
0
Section 17 A/D Converter
CH1
R/W
1
0
REJ09B0219-0100
CH0
R/W
0
0