dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 81

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4
Address Generation Unit
This chapter describes the architecture and the operation of the address generation unit (AGU). The
address generation unit is the block where all address calculations are performed. It contains two
arithmetic units — a modulo arithmetic unit for complex address calculations and an
incrementer/decrementer for simple calculations. The modulo arithmetic unit can be used to calculate
addresses in a modulo fashion, automatically wrapping around when necessary. A set of pointer registers,
special-purpose registers, and multiple buses within the unit allow up to two address updates or a memory
transfer to or from the AGU in a single cycle.
The capabilities of the address generation unit include the following operations:
Note that in the cases where the address generation unit is generating one or two addresses to access X data
memory, the program controller generates a second or third address used to concurrently fetch the next
instruction.
The AGU provides many different addressing modes, which include the following:
Freescale Semiconductor
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Provide one address to X data memory on the XAB1 bus
Post-update an address after providing the original address value on XAB1 bus
Calculate an effective address which is then provided on the XAB1 bus
Provide two addresses to X data memory on the XAB1 and XAB2 buses and post-update both
addresses
Provide one address to program memory for program memory data accesses and post-update the
address
Increment or decrement a counter during normalization operations
Provide a conditional register move (Tcc instruction)
Indirect addressing with no update
Indirect addressing with post-increment
Indirect addressing with post-decrement
Indirect addressing with post-update by a
register
Indirect addressing with index by a 16-bit
offset
Indirect addressing with index by a 6-bit
offset
Indirect addressing with index by a register
Address Generation Unit
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Immediate data
Immediate short data
Absolute addressing
Absolute short addressing
Peripheral short addressing
Register direct
Implicit
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