dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 120

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Program Controller
Details of interrupt arbitration and the exception processing state are discussed in Section 7.3, “Exception
Processing State,” on page 7-5. The reset processing state is discussed in Section 7.1, “Reset Processing
State,” on page 7-1.
5.1.4
The looping control unit provides hardware dedicated to support loops, which are frequent constructs in
DSC algorithms.
The repeat instruction (REP) loads the 13-bit LC register with a value representing the number of times the
next instruction is to be repeated. The instruction to be repeated is only fetched once per loop, so power
consumption is reduced, and throughput is increased when running from external program memory by
decreasing the number of external fetches required.
The DO instruction loads the 13-bit LC register with a value representing the number of times the loop
should be executed, loads the LA register with the address of the last instruction word in the loop (fetched
only once per loop), and sets the loop flag (LF) bit in the SR. The top-of-loop address is stacked on the
HWS so the loop can be repeated with no overhead. When the LF in the SR is asserted, the loop state
machine will compare the PC contents to the contents of the LA to determine if the last instruction word in
the loop was fetched. If the last word was fetched, the LC contents are tested for one. If LC is not equal to
one, then it is decremented, and the contents of the HWS (the address of the first instruction in the loop)
are read into the PC, effectively executing an automatic branch to the top of the loop. If the LC is equal to
one, then the LF in the SR is restored with the contents of the OMR’s nested looping (NL) bit, the
top-of-loop address is removed from the HWS, and instruction fetches continue at the incremented PC
value (LA + 1).
Nested loops are supported by stacking the address of the first instruction in the loop (top of loop) in the
HWS and copying the LF bit into the OMR’s NL bit prior to the execution of the first instruction in the
loop. The user, however, must explicitly stack the LA and LC registers as described in Section 8.6.4,
“Nested Loops,” on page 8-22.
Looping is described in more detail in Section 5.3, “Program Looping,” and Section 8.6, “Loops,” on page
8-20.
5.1.5
The loop counter (LC) is a special 13-bit down counter used to specify the number of times to repeat a
hardware program loop (DO and REP loops). When the end of a hardware program loop is reached, the
contents of the loop counter register are tested for one. If the loop counter is one, the program loop is
terminated. If the loop counter is not one, it is decremented by one and the program loop is repeated.
The loop counter may be read and written under program control. This gives software programs access to
the value of the current loop iteration. It also allows for saving and restoring the LC to and from the
software stack when nesting DO loops in software. Note that since the LC is only a 13-bit counter, it is
zero-extended when read; when written, the top three bits of the source word are ignored. This is shown in
Figure 5-3 on page 5-5.
5-4
Looping Control Unit
Loop Counter
DSP56800 Family Manual
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