dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 323

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

LSRR
Operation:
S1 >> S2 → D
Description: Logically shift the source operand S1 to the right by the value contained in the lowest 4 bits of S2, and
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Timing:
Memory:
Freescale Semiconductor
Operation
LSRR
Before Execution
A2
0
store the result in the destination (D). For 36-bit destinations, only the MSP is shifted and the LSP is
cleared, with zero extension from bit 31 (the FF2 portion is ignored). The result is not affected by the
state of the saturation bit (SA).
LSRR
Prior to execution, the Y1 register contains the value to be shifted ($AAAA), and the X0 register con-
tains the amount by which to shift ($0004). The contents of the destination register are not important
prior to execution because they have no effect on the calculated value. The LSRR instruction logically
shifts the value $AAAA four bits to the right and places the result in the destination register (A). Since
the destination is an accumulator, the extension word (A2) is filled with sign extension, and the LSP
(A0) is set to zero.
2 oscillator clock cycles
1 program word
LF
15
3456
A1
14
*
N
Z
13
*
Y1,X0,FDD
Y0,X0,FDD
Y1,Y0,FDD
Y0,Y0,FDD
A1,Y0,FDD
B1,Y1,FDD
Y1
X0
Operands
— Set if MSB of result is set
— Set if result equals zero
Y1,X0,A
12
*
Multi-Bit Logical Right Shift
MR
11
AAAA
*
3456
0004
A0
10
*
Instruction Set Details
I1
9
C
2
Assembler Syntax:
LSRR
I0
8
W
1
SZ
7
After Execution
; right shift of 16-bit Y1 by X0
Logical shift right of the first operand by value specified
in four LSBs of the second operand; places result in FDD
(when result is to an accumulator F, zero extends into F2)
A2
6
L
0
5
E
S1,S2,D
0AAA
U
4
CCR
A1
N
3
Y1
X0
Z
Comments
2
V
1
AAAA
0000
0004
A0
C
0
LSRR
A-93