dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 445

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Saturation bit (SA) 5-11
SBC A-150
SD stop delay bit 5-12
shift operations 8-8
Signed Multiply and Round MPYR A-124
Signed Multiply MPY A-121
Signed Unsigned Multiply MPYSU A-127
software interrupt sources
Software Interrupt SWI A-156
software stack 5-13
SP, see Stack Pointer Register (SP)
SR, see Status Register (SR)
Stack Pointer Register (SP) 4-4
Start Hardware Do Loop DO A-71
Status Register (SR) 5-6
STOP A-152
stop delay (SD) 5-12
STOP instruction 7-19
Stop Instruction Processing STOP A-152
stop processing state 7-1
SUB A-153
Subtract Long with Carry SBC A-150
Subtract SUB A-153
subtraction
SWI A-156
SZ condition bit 5-8
T
TAP, see test access port (TAP)
Tcc A-157
test access port (TAP) 9-2
Test Accumulator TST A-161
Test Bitfield and Change BFCHG A-47
Test Bitfield and Clear BFCLR A-49
Test Bitfield and Set BFSET A-51
Test Bitfield High BFTSTH A-53
Test Bitfield Low BFTSTL A-55
Test Register or Memory TSTW A-163
TFR A-159
illegal instruction (III) 7-11
software interrupt (SWI) 7-11
carry bit (C) 5-7
extension bit (E) 5-8
interrupt mask bits (I1 and I0) 5-8
limit bit (L) 5-8
loop flag bit (LF) 5-9
negative bit (N) 5-7
overflow bit (V) 5-7
reserved bits 5-9
size bit (SZ) 5-8
unnormalized bit (U) 5-8
zero bit (Z) 5-7
fractional 3-18
multi-precision 3-23
,
A-7
,
7-19
DSP56800 Family Manual
time-critical loops 8-29
Transfer Conditionally Tcc A-157
Transfer Data ALU Register TFR A-159
TST A-161
TSTW A-163
two’s-complement rounding 3-31
U
U condition bit 5-8
unsigned arithmetic 3-22
unsigned load of an accumulator 8-7
V
V condition bit 5-7
W
WAIT A-165
Wait for interrupt WAIT A-165
wait processing state 7-1
X
X0 input register 3-2
XAB1, see external address bus one (XAB1)
XAB2, see external address bus two (XAB2)
XCHG register exchange operation 8-6
XDB2, see external data bus two (XDB2)
Y
Y0 input register 3-2
Y1 input register 3-2
Z
Z condition bit 5-7
addition 3-22
condition code computation 3-22
multiplication 3-22
subtraction 3-22
,
,
,
A-10
A-9
A-10
,
,
,
3-4
3-4
3-4
,
7-17
Index-v