dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 33

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

The multiply-accumulation (MAC) operation is the fundamental operation used in DSC. The DSP56800
Family of processors has a dual Harvard architecture optimized for MAC operations. Figure 1-6 on
page 1-8 shows how the DSP56800 architecture matches the shape of the MAC operation. The two
operands, c( ) and x( ), are directed to a multiply operation, and the result is summed. This process is built
into the chip by allowing two separate data-memory accesses to feed a single-cycle MAC. The entire
process must occur under program control to direct the correct operands to the multiplier and save the
accumulated result as needed. Since the memory and the MAC are independent, the DSC can perform two
memory moves, a multiply and an accumulate, and two address updates in a single operation. As a result,
many DSC benchmarks execute very efficiently for a single-multiplier architecture.
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The high throughput of the DSP56800 Family processors makes them well-suited for wireless and wireline
communication, high-speed control, low-cost voice processing, numeric processing, and computer and
audio applications. The main features that contribute to this high throughput include the following:
Freescale Semiconductor
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Speed—The DSP56800 supports most mid-performance DSC applications.
Precision—The data paths are 16 bits wide, providing 96 dB of dynamic range; intermediate results
held in the 36-bit accumulators can range over 216 dB.
Parallelism—Each on-chip execution unit, memory, and peripheral operates independently and in
parallel with the other units through a sophisticated bus system. The data ALU, AGU, and program
controller operate in parallel so that the following can be executed in a single instruction:
— An instruction pre-fetch
— A 16-bit x 16-bit multiplication
— A 36-bit addition
— Two data moves
— Two address-pointer updates using one of two types of arithmetic (linear or modulo)
— Sending and receiving full-duplex data by the serial ports
— Timers continuing to count in parallel
Flexibility—While many other DSCs need external communications circuitry to interface with
peripheral circuits (such as A/D converters, D/A converters, or host processors), the DSP56800
Family provides on-chip serial and parallel interfaces that can support various configurations of
memory and peripheral modules. The peripherals are interfaced to the DSP56800 core through a
peripheral interface bus, designed to provide a common interface to many different peripherals.
Sophisticated debugging— Freescale’s On-Chip Emulation technology (OnCE) allows simple,
inexpensive, and speed-independent access to the internal registers for debugging. OnCE tells
application programmers exactly what the status is within the registers, memory locations, and even
the last instructions that were executed.
Phase-locked loop (PLL)–based clocking—The PLL allows the chip to use almost any available
external system clock for full-speed operation while also supplying an output clock synchronized
to a synthesized internal core clock. It improves the synchronous timing of the processors’ external
memory port, eliminating the timing skew common on other processors.
Invisible pipeline—The three-stage instruction pipeline is essentially invisible to the programmer,
allowing straightforward program development in either assembly language or high-level
languages such as C or C++.
Summary of Features
Introduction
Summary of Features
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