dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 175

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

7.3.5.2
Other interrupt sources include the following:
An overflow of the hardware stack (HWS) causes a stack overflow interrupt that is vectored to P:$000A
(see Section 5.1.7, “Hardware Stack,” on page 5-6). Encountering the stack overflow condition means that
too many DO loop addresses have been stacked and that the oldest top-of-loop address has been lost. The
stack error is non-recoverable. The stack error condition refers to hardware stack overflow and does not
affect the software stack pointed to by the stack pointer (SP) register in any manner.
The OnCE trap interrupt is an interrupt that can be set up in the OnCE debug port accessible through the
JTAG pins. This gives the debug port the capability to generate an interrupt on a trigger condition such as
the matching of an address in the OnCE port (see Section 9.3, “OnCE Port,” on page 9-4 for more
information).
In addition to these sources there are seven general-purpose interrupt channels, Ch0 through Ch6, available
for use by on-chip peripherals such as timers and serial ports. Each channel can independently generate an
interrupt request, each can be individually masked, and each channel can have one or more dedicated
locations in the interrupt vector table. Typically, one channel is assigned to each on-chip peripheral, but, in
cases where there are more than seven peripherals that can generate interrupts, it is possible to put more
than one peripheral on a single interrupt channel.
7.3.5.3
The two software interrupt sources are listed below:
An SWI is a non-maskable interrupt that is serviced immediately following the SWI instruction execution
(that is, no other instructions are executed between the SWI instruction and the JSR instruction found in
the interrupt vector table). The difference between an SWI and a JSR instruction is that the SWI sets the
interrupt mask to prevent level 0–maskable interrupts from being serviced. The SWI’s ability to mask out
lower-level interrupts makes it very useful for setting breakpoints in monitor programs or for making a
system call in a simple operating system. The JSR instruction does not affect the interrupt mask.
The illegal instruction interrupt is also a non-maskable interrupt (priority level 1). It is serviced
immediately following the execution or attempted execution of an illegal instruction (an undefined
operation code). Illegal exceptions are fatal errors. The JSR located in the illegal instruction interrupt
vector will stack the address of the instruction immediately after the illegal instruction.
Freescale Semiconductor
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Stack error interrupt — priority level 1
OnCE trap — priority level 1
All on-chip peripherals (such as timers and serial ports) — priority level 0
Software interrupt (SWI) — priority level 1
Illegal instruction interrupt (Ill) — priority level 1
DSC Core Hardware Interrupt Sources
DSC Core Software Interrupt Sources
Interrupts and the Processing States
Exception Processing State
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