dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 40

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Core Architecture Overview
Data transfer between the data ALU and the X data memory uses the CGDB when one memory access is
performed. When two simultaneous memory reads are performed, the transfers use the CGDB and the
XDB2. All other data transfers occur using the CGDB, except transfers to and from peripherals on
DSP56800-based devices that implement the IP-BUS or PGDB peripheral data bus. Instruction word
fetches occur simultaneously over the PDB. The bus structure supports general register-to-register moves,
register-to-memory moves, and memory-to-register moves, and can transfer up to three 16-bit words in the
same instruction cycle. Transfers between buses are accomplished in the bus and bit-manipulation unit. As
a general rule, when any register less than 16 bits wide is read, the unused bits are read as zeros. Reserved
and unused bits should always be written with zeros to insure future compatibility.
2.2
The DSP56800 has a dual Harvard memory architecture, with separate program and data memory spaces.
Each address space supports up to 2
address space allow for simultaneous accesses to both program memory and data memory. There is also a
support for a second read-only data path to data memory. In DSP56800 Family devices that implement this
second bus, it is possible to initiate two simultaneous data read operations, allowing for a total of three
parallel memory accesses.
Locations $0 through $007F in the program memory space are available for reset and interrupt vectors.
Peripheral registers are located in the data memory address space as memory-mapped registers. This
peripheral space can be located anywhere in the data address space, although the address range
$FFC0–$FFFF provides faster access when using an addressing mode optimized for this region; however,
the location of the peripheral space is dependent on the specific peripheral bus implementation of the
DSP56800 core. See Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on page 4-23 for
more information.
2-6
Memory Architecture
$FFFF
$7F
NOTE: The placement of the peripheral space is dependent on the specific system
$0
range and are accessed with standard X-memory reads and writes.
peripheral registers may be memory mapped into any data (X) memory address
implementation for the DSP56800 core. When the IP-BUS interface is used,
Interrupt
Program
Vectors
Memory
Space
Figure 2-2. DSP56800 Memory Spaces
16
(65,536) memory words. Dedicated address and data buses for each
127
DSP56800 Family Manual
64K or 2
0
16
$FFC0
$FFFF
$0
Optimized for
Peripherals
Memory
X Data
Space
Freescale Semiconductor
64K or 2
(64K - 64)
0
16