dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 152

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Instruction Set Introduction
6-20
Note:
Operation
Tcc
Operation
IMPY16
MACR
IMPY
MAC
MPY
The Tcc instruction does not allow the following condition codes: HI, LS, NN, and NR.
or
Source
DD
DD
Data ALU Transfer
A
A
B
B
Destination
Table 6-22. Conditional Register Transfer Instructions
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
B
A
B
A
F
F
Y1,X0,FDD
Y0,X0,FDD
Y1,Y0,FDD
Y0,Y0,FDD
A1,Y0,FDD
B1,Y1,FDD
Operands
Table 6-23. Data ALU Multiply Instructions
(parallel)
(parallel)
(parallel)
Source
DSP56800 Family Manual
R0
R0
R0
AGU Transfer
(No transfer)
(No transfer)
(No transfer)
Destination
C
2
2
2
2
R1
R1
R1
W
1
1
1
1
Integer 16x16 multiply with 16-bit result
When the destination is an accumulator F, the F0
portion is unchanged by the instruction.
Note: Assembler also accepts first two operands
when they are specified in opposite order.
Fractional multiply accumulate; multiplication
result optionally negated before accumulation.
Note: Assembler also accepts first two operands
when they are specified in opposite order.
Refer to Table 6-35 & Table 6-36.
Fractional MAC with round, multiplication result
optionally negated before addition.
Note: Assembler also accepts first two operands
when they are specified in opposite order.
Refer to Table 6-35 & Table 6-36.
Fractional multiply where one operand is optionally
negated before multiplication.
Note: Assembler also accepts first two operands
when they are specified in opposite order.
Refer to Table 6-35 & Table 6-36.
C
2
W
1
Conditionally transfer one register
Conditionally transfer one data
ALU register and one AGU register
Comments
Freescale Semiconductor
Comments