dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 266

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

ANDC
Operation:
#xxxx•X:<ea> → X:<ea>
#xxxx•D → D
where • denotes the logical AND operator
Implementation Note:
Description: Logically AND a 16-bit immediate data value with the destination operand, and store the results back
Example:
Explanation of Example:
Condition Codes Affected:
A-36
This instruction is an alias to the BFCLR instruction, and assembles as BFCLR with the 16-bit imme-
diate value inverted (one’s-complement) and used as the bit mask. It will disassemble as a BFCLR in-
struction.
into the destination. C is also modified as described in the following discussion. This instruction per-
forms a read-modify-write operation on the destination and requires two destination accesses.
ANDC
Prior to execution, the 16-bit X memory location X:$A000 contains the value $C3FF. Execution of the
instruction tests the state of bits: 0, 2, 4, 6, 8, 10, 12, and 14 in X:$A000. It clears C (because not all
the bits tested were set in destination X:$A000). Result from logical AND is written back to the tested
location.
For destination operand SR:
For other destination operands:
Before Execution
X:$A000
LF
15
SR
14
*
?
L
C
13
*
— Cleared as defined in the field and if specified in the field
— Set if data limiting occurred during 36-bit source move
— Set if all bits specified by the mask are set
#$5555,X:$A000
12
C3FF
0301
*
MR
Cleared if not all bits specified by the mask are set
Logical AND, Immediate
11
*
DSP56800 Family Manual
10
*
I1
9
Assembler Syntax:
ANDC
ANDC
I0
8
SZ
7
L
6
; AND with immediate data
5
E
After Execution
X:$A000
#iiii,X:<ea>
#iiii,D
U
4
CCR
SR
N
3
2
Z
4155
0300
V
1
Freescale Semiconductor
C
0
ANDC