dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 141

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

See Section 8.1.1, “Jumps and Branches,” on page 8-2 for other instructions that can be synthesized.
6.4.4
The looping instructions establish looping parameters and initiate zero-overhead program looping. They
allow looping on a single instruction (REP) or a block of instructions (DO). For DO looping, the address of
the first instruction in the program loop is saved on the hardware stack to allow no-overhead looping. The
last address of the DO loop is specified as a 16-bit absolute address. No locations in the hardware stack are
required for the REP instruction. The ENDDO instruction is used only when breaking out of the loop;
otherwise, it is better to use
Termination of a DO Loop,” on page 8-25.
Table 6-6 lists the loop instructions.
6.4.5
The move instructions move data over the various data buses: CGDB, IP-BUS (or PGDB), XDB2, and
PDB. Move instructions do not affect the condition code register, except for the limit bit if limiting is
performed when reading a data ALU accumulator register. These instructions do not allow optional data
transfers. In addition to the following move instructions, there are parallel moves that can be used
simultaneously with many of the arithmetic instructions. The parallel moves are shown in Table 6-35 on
Freescale Semiconductor
Looping Instructions
Move Instructions
Due to instruction pipelining, if an AGU register (Rj, N, SP, or M01) is
directly changed with a bit-field instruction, the new contents may not be
available for use until the second following instruction (see the restrictions
discussed in Section 4.4, “Pipeline Dependencies,” on page 4-33).
Instruction
Instruction
BFTSTH
ENDDO
BRCLR
BRSET
NOTC
EORC
ORC
REP
DO
MOVE #1,LC
Table 6-5. Bit-Field Instruction List (Continued)
Start hardware loop
Disable current loop and unstack parameters
Repeat next instruction
Bit-field test high
Branch if selected bits are set
Branch if selected bits are clear
Logical exclusive OR with immediate data
Logical complement on memory location and registers
Logical inclusive OR with immediate data
Table 6-6. Loop Instruction List
Instruction Set Introduction
. This is discussed in more detail in Section 8.6.6, “Early
NOTE:
Description
Description
Instruction Groups
6-9