dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 190

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Software Techniques
8.1.1.4
Although there is no instruction for jumping or branching on overflow, such an operation can be emulated
as shown in the following code. Note that the carry bit will be destroyed by this operation since it receives
the result of the BFTSTH instruction. The following code shows JVS and BVC.
; JVS Operation
; Emulated in 5 Icyc (4 Icyc if false), 4 Instruction Words
; BVC Operation
; Emulated in 5 Icyc (4 Icyc if false), 3 Instruction Words
8.1.1.5
Jumping and branching using some of the other condition codes (PL, MI, EC, ES, LMC, LMS) can be
accomplished in the same manner as for overflow; see Section 8.1.1.4, “JVS, JVC, BVS, and BVC
Operations.” Remember that this technique destroys the value in the carry bit. The following code shows
JPL and BES.
; JPL Operation
; Emulated in 5 Icyc (4 Icyc if false), 4 Instruction Words
; BES Operation
; Emulated in 5 Icyc (4 Icyc if false), 3 Instruction Words
Similar code can be written for JMI, JEC, JES, JLMC, JLMS, BPL, BMI, BEC, BLMC, and BLMS. The
JLMS and JLMC are used for “jump if limit set” and “jump if limit clear,” respectively; this is done to
avoid any confusion with the JLS (“jump if lower or same”) instruction.
8.1.2
The NEGW operation can be used to negate the upper two registers of the accumulator. The NEG
operation can be used to negate the X0, Y0, or Y1 data ALU registers, negate an AGU register, or negate a
memory location.
8.1.2.1
The NEGW operation can be emulated as shown in the following code:
; 20-bit NEGW Operation
; Operates on EXT:MSP, Clears LSP, 3 Icyc
This correctly negates the upper 20 bits of the accumulator, but also destroys the A0 register.
8-4
BFTSTH
JCS
BFTSTH
BCC
BFTSTH
JCC
BFTSTH
BCS
MOVE
NEG
Negation Operations
JVS, JVC, BVS, and BVC Operations
Other Jumps and Branches on Condition Codes
NEGW Operation
#$0002,SR
label
#$0002,SR
label
#$0008,SR
label
#$0020,SR
label
#0,A0
A
Example 8-4. JVS, JVC, BVS and BVC
Example 8-5. JPL and BES
DSP56800 Family Manual
; Clear LSP
; Now negates upper 20 bits of accumulator
; since A0 = 0
; Test V bit in SR
; 16-bit jump address allowed
; Test V bit in SR
; 7-bit signed PC relative offset allowed
; Test the N bit in SR
; 16-bit jump address allowed
; Test E bit in SR
; 7-bit signed PC relative offset allowed
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