dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 291

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

CLR
Operation:
0 → D
0 → D
Description: Set the A or B accumulator to zero. Data limiting may occur during a parallel write. The 16-bit registers
Implementation Note:
Example:
Explanation of Example:
Condition Codes Affected:
Note:
Freescale Semiconductor
A Before Execution
A2
2
(single parallel move)
are cleared using the MOVE instruction.
When a 16-bit register is used as the operand for CLR, this instruction is actually assembled as a
MOVE #0,<register> instruction. It will disassemble as MOVE instruction.
CLR
Prior to execution, the 36-bit A accumulator contains the value $2:3456:789A. Execution of the
CLR A instruction clears the 36-bit A accumulator to zero.
The condition codes are only affected if the destination of the CLR instruction is one of the two 36-bit
accumulators (A or B).
LF
15
3456
14
A1
*
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
13
*
— Set if data limiting has occurred during parallel move
— Always cleared if destination is a 36-bit accumulator
— Always set if destination is a 36-bit accumulator
— Always cleared if destination is a 36-bit accumulator
— Always set if destination is a 36-bit accumulator
— Always cleared if destination is a 36-bit accumulator
A
12
*
MR
11
*
789A
A0
Clear Accumulator
10
A,X:(R0)+
*
Instruction Set Details
I1
9
Assembler Syntax:
CLR
CLR
I0
8
SZ
7
; save A into X data memory before
;
A After Execution
L
6
A2
0
E
5
clearing it
D
D
U
4
CCR
0000
A1
N
3
Z
2
V
(single parallel move)
1
0000
C
0
A0
CLR
A-61