dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 200

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Software Techniques
Once all these questions have been answered, it is possible to select the appropriate division algorithm. The
fractional algorithms support a 32-bit signed dividend, and the integer algorithms support a 31-bit signed
dividend. All algorithms support a 16-bit divisor.
Note that the most general division algorithms are the fractional and integer algorithms for four-quadrant
division that generate both a quotient and a remainder. These take the largest number of instruction cycles
to complete and use the most registers.
For extended precision division, where the number of quotient bits required is more than 16, the DIV
instruction and routines presented in this section are no longer applicable. For further information on
division algorithms, consult the following references (or others as required):
Theory and Application of Digital Signal Processing, Lawrence R. Rabiner and Bernard Gold
(Prentice-Hall: 1975), pages 524–530.
Computer Architecture and Organization, John Hayes (McGraw-Hill: 1978), pages 190–199.
8.4.1
The algorithms in the following code are the fastest and take the least amount of program memory. In order
to use these algorithms, it must be guaranteed that both the dividend and divisor are both positive, signed,
two’s-complement numbers. One algorithm is presented for the division of fractional numbers and a
second is presented for the division of integer numbers. Both algorithms generate the correct positive
quotient and positive remainder.
; Division of Fractional, Positive Data (B1:B0 / X0)
;
Skip_Corr:
; Division of Integer, Positive Data (B1:B0 / X0). Registers used: Y1
;
8-14
Results: B1 = Remainder, B0 = Quotient, X0 (not changed)
Results: B1 = Remainder, B0 = Quotient, X0 (not changed)
TSTW
REP
DIV
TST
BGE
ADD
ASL
TSTW
REP
DIV
MOVE
ADD
ASR
MOVE
Positive Dividend and Divisor with Remainder
The REP instruction is not interruptible; therefore, if user requires a
interruptible sequence on the division, it is advisable to use the DO
instruction or perform loop unrolling on the REP sequences.
B
#16
X0,B
B
Skip_Corr
X0,B
B
B
#16
X0,B
B0,Y1
X0,B
B
Y1,B0
DSP56800 Family Manual
; TSTW always clears carry bit and more efficient
;
; Carry bit must be clear for first DIV
; Form positive quotient in B0
; Verify if remainder needs correction
;
; Correct the remainder stored in B1
; At this point, positive quotient in B0
;
; Shift of dividend required for integer division
; TSTW always clears carry bit and more efficient
;
; Carry bit must be clear for first DIV
; Form positive quotient in B0
; Save quotient in Y1, (at this point, remainder
;
; Correct remainder in B1
; Required for correct integer remainder
; At this point, positive quotient in B0
;
and positive remainder in B1. End of Algorithm.
and positive remainder in B1. End of Algorithm.
than using BFCLR
skip correction if not required
than using BFCLR
is not yet correct).
NOTE:
#$0001,SR
#$0001,SR
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